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Sensoray 2600 Programming Guide 38 Gateway Action Scheduling

7.6.1 Type-Specific Errors

In addition to the common IOM status bit flags (STATUS_RST and STATUS_CERR), this IOM type supports the following

type-specific flags. If any of these flags are asserted, a transaction error of type GWERR_IOMSPECIFIC will be generated:

7.6.2 Analog Input Modes

Input mode registers allow to set timing parameters of the analog-digital conversion for each channel. The enumerated

oversample ratio settings, speed multiplier and reference voltages type names are defined in the App2600.h

header file.

7.6.3 S26_Sched2612_SetMode()

Schedules the programming of the measurement mode for one channel on model 2612 IOM.

Prototype: u32 S26_Sched2612_SetMode( XACT x, IOMPORT IomPort, u8 chan, u32 mode );

The mode parameter contains the OSR (oversample ratio) selector and speed multiplier enable bit:

Returns: Error code as described in section 5.5. Zero is returned if the operation was successful.

Symbolic Name Description

STATUS_2612_OVERFLOW

Differential input voltage exceeds ADC positive input limit.

STATUS_2612_UNDERFLOW

Differential input voltage exceeds ADC negative input limit.

STATUS_2612_EEPROM

EEPROM read/write error. This flag will be asserted if the 2412’s internal EEPROM checksum is invalid.

This can happen if S26_2612_RestoreCalibrations() is called before

S26_2612_RestoreCalibrations() has been called at least once for the target channel.

Parameter Type Description

x void *

Transaction handle obtained from S26_SchedOpen().

IomPort u8

The IOM port number (on the MM) to which the target IOM is connected.

chan u8

The channel number that is to be programmed. Legal values range from 0 to 3.

mode u32

One of the OSR symbolic constants. To use the speed multiplier mode, the MODE_2X

symbolic constant must be ORed with the OSR.

031

0 0 0 0 0 0 0 0

OSRSEL

The OSRSEL field selects the oversample ratio, which in

turn configures a number of other behavioral attributes.

Any of the following values may be specified:

The M bit enables the speed multiplier when set to logic

one, and it disables the multiplier when set to zero.

When enabled, the speed multiplier doubles the

conversion rate at the expense of one additional cycle

of latency.

The most significant nibble must be set to 0xA. All

other bits, which are reserved for future use, must be

set to zero.

OSRSEL OSR

RMS

Noise

(µV)

Convert

Rate

(Hz)

First

Notch

(Hz)

–3dB

Point

(Hz)

Effective

Bits

1 64 23 3515.6 28125 1696 17.0

2 128 4.5 1757.8 14062.5 848 20.1

3 256 2.8 878.9 7031.3 424 20.8

4 512 2.0 439.5 3515.6 212 21.3

5 1024 1.4 219.7 1757.8 106 21.8

6 2048 1.1 109.9 878.9 53 22.1

7 4096 0.72 54.9 439.5 26.5 22.7

8 8192 0.53 27.5 219.7 13.2 23.2

9 16384 0.35 13.75 109.9 6.6 23.8

15 32768 0.28 6.875 54.9 3.3 24.1

M 0 0 0 0 0 0 0 0 0 0 0

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 76 77

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