Sensoray 526 Manual do Utilizador

1 PC/104 Multifunction I/O Board Hardware Manual Model 526 | Rev.B | February 2009

10 RegisterWrite (0x14, 0x0001); //load Preload Register high word RegisterWrite (0x12, 0x3C68); //load Preload Register low word Step 2. Reset the

11 To change the duty cycle steps 1-2 have to be repeated with the new preload register values. Interrupt Timer The interrupt timer provides a w

12 Watchdog enable/disable Watchdog enable/disable is controlled by bit [3] of the Watchdog Timer Control register and jumper 1 of J4. Shunt in p

13 D/A Converter Model 526 implements a 4-channel 16-bit D/A converter. Each channel has an individual preload buffer. Preload buffers are accessed

14 −−⋅=00CCCCVVrefmeasrefmeas, where refV- the actual value of the on-board 10V reference (from the EEPROM); measC- ADC reading correspondin

15 Digital I/O Digital I/O on model 526 consists of 8 signals, which can be configured as inputs or outputs in groups of 4: DIO group 1 (DIO0-3) and

16 Calibration EEPROM An on-board EEPROM is provided for calibration data storage. Data from the EEPROM is read by using a set of 2 registers: EEPRO

17 Configuration Jumpers A set of configuration jumpers (J1) allows selection of board’s base address and interrupt line (See Fig.1). Jumpers marke

18 Digital connector (J5) Pin Signal Pin Signal 1 Clock A 0 - 2 Clock A 0 + 3 Clock B 0 - 4 Clock B 0 + 5 Index 0 - 6 Index 0 + 7 Coun

19 Registers Register Map Register addresses are relative to the base address selected with address jumpers (ADDR 15 – 6). All register accesses ar

2 Table of Contents TABLE OF CONTENTS... 2 LIM

20 Timer Control Register 0x00 Bits Type Default Description [15:8] WO 0x00 Timer preload data in 100 us ticks. [7:2] UU XXXXXX Reserved

21 DAC Control Register 0x04 Bits Type Default Description [15:4] UU X Reserved. [3] WO 0 DAC reset. Writing a 1 to this bit resets all D

22 ADC Control Register 0x06 Bits Type Default Description [15] WO 0 Input multiplexor settling delay: 0 – no delay; 1 – 12 µs delay. [14:5]

23 Digital I/O Control Register 0x0A Bits Type Default Description [15] WO 0 DIO(3) interrupt condition: 0 – interrupt on a rising edge; 1 –

24 Interrupt Enable Register 0x0C Bits Type Default Description [15] WO 0 DIO7 interrupt enable. [14] WO 0 DIO6 interrupt enable. [13] WO

25 Miscellaneous Register 0x10 Bits Type Default Description [15:1] UU X Reserved. [0] RW 0 LED control. A 0 turns the LED on, a 1 turns i

26 Counter Mode Register 0x16 – counter 0, 0x1E – counter 1, 0x26 – counter 2, 0x2E – counter 3. Bits Type Default Description [15] UU X Rese

27 Notes. 1. In “Latch on read” mode data from the counter is latched on the read access to the Counter data low word register. Thus the low word h

28 EEPROM Data Register 0x32 Bits Type Default Description [15:0] RW 0x0000 EEPROM data. Read accesses return the last value read from EEPROM

29 Specifications Parameter Value Units Notes D/A Converter Number of channels 4 Resolution 16 bits Upload time, max 8 µs Sett

3 Counter Mode Register... 26 Counter Control/Status R

4 Limited warranty Sensoray Company, Incorporated (Sensoray) warrants the hardware to be free from defects in material and workmanship and perform t

5 Introduction Model 526 is a PC/104 multifunctional I/O board with the following features: • Four 24-bit programmable counters. Inputs could be dr

6 Fig.1. Model 526 board outline.

7 Programmable Counters Model 526 contains 4 identical 24-bit up/down counters with enable and preload. The block diagram of one of the counters is

8 • quadrature x2 (both edges of CLKA); • quadrature x4 (both edges of both CLKA and CLKB); In normal mode the clock sources are: • CLKA↑; • CL

9 determined by the state of the RTGL signal: PR0 when RTGL is low, PR1 when RTGL is high. The autoload occurs under a programmable combination of