
20
Timer Control Register
0x00
Bits Type Default Description
[15:8] WO 0x00 Timer preload data in 100 us ticks.
[7:2] UU XXXXXX Reserved
[1] WO 0 Timer mode:
0 – manual restart;
1 – auto restart.
[0] WO 0 Manual restart. Writing a 1 restarts the timer if [1] is 0. Bit [0]
of the Interrupt Status register is set to 1 when timer expires.
Watchdog Timer Control Register
0x02
Bits Type Default Description
[15:5] UU X Reserved.
[4] WO 0 Solid-state relay control signal polarity: 0 – normal (active
when timed out), 1 – inverted (active when not timed out).
(See Note 2).
[3] WO 0 Watchdog timer software enable: writing a 1 enables, writing a
0 disables the watchdog timer (see Note 3).
[2:0] WO 000 Timeout interval:
000 – 16 sec;
001 – 8 sec;
010 – 4 sec;
011 – 2 sec;
100 – 1 sec;
101 – 0.5 sec;
110 – 0.25 sec;
111 – 0.125 sec.
Notes:
1. Reading the Watchdog Timer Control register “tags” the watchdog (restarts the count). The
data returned by read access is undefined.
2. The meaning of bit [4] corresponds to the case when a shunt in position 2 of jumper J4 is
NOT installed. If the shunt is installed, the meaning of bit [4] is reversed: 0 corresponds to
normal, and 1 – to inverted polarity of the solid-state relay control signal.
3. The meaning of bit [3] corresponds to the case when a shunt in position 1 of jumper J4 is
NOT installed. If the shunt is installed, the meaning of bit [3] is reversed: 0 enables, and 1
disables the watchdog timer. Thus installing the shunt enables the watchdog timer by default
after the power up.
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